1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more specifically, to an improvement in an operation executed from the time at which a word line is selected to the time at which information stored in a cell is output to a data line, and an improvement in a power supply related to the above operation in a dynamic random access memory device, for the purposes of increasing the operation speed and reducing power consumption.
Nowadays, semiconductor memory devices such as DRAM devices have an internal power supply, which generates an internal voltage by lowering an external power supply voltage for reduced power consumption. 0n the other hand, it is necessary to boost the word line voltage up over the internal power supply voltage (sometimes the external power supply voltage) in the write operation in order to store sufficient information in the cells because of reductions in the storage capacities of the cells resulting from reductions in their size.
Further, in order to retain the information written into the cells for long periods of time, it is necessary to suppress current leaks taking place in the diffusion layers connected to the storage electrodes of the cells. For this purpose, a technology for applying a negative voltage to the back gates of the cell transistors has been employed in practice.
Furthermore, an internal power supply is needed because the pre-charge voltage on the bit lines and the voltage on the cell plate (an opposed electrode) opposite to the storage electrodes are set approximately equal to half the write voltage of the cells. Actual memory devices have several internal voltage generators. Normally, the internal power supply voltages are generated by pumping or resistance division. Hence, reduction in power consumption is prevented by currents that flow in internal power supply voltage generated in the standby mode.
Generally, enhancement-type N-channel MOSFETs are used to form cells in order to increase the operation speed. In a case where the pre-charge voltages on the bit lines are half the write voltage of the cells and a 1 is stored in a cell, the information does not appear on the data line when the voltage of the word line exceeds the sum of the pre-charge voltage and the threshold voltage of the N-channel MOSFET. Originally, the loads of the word lines are heavy and prevent the high-speed operation. Hence, the threshold voltage of the N-channel MOSFET has a great impact.
2. Description of the Prior Art
FIG. 1 is a circuit diagram of the essential parts of a conventional semiconductor memory device. In this figure, n memory cells (n is an integer equal to or greater than 1) are connected to a data line 13. Each of the cells has a cell capacitor (capacitance element) 11 and an enhancement-type N-channel MOSFET (cell transistor) 12, which functions as a switching element. One end of the cell capacitor 11 is connected to the drain (source) of the corresponding cell transistor 12, and the other end thereof is connected to a reference point (set to, for example, VCC/2 where VCC denotes the power supply voltage). The source (drain) of the cell transistor 12 is connected to the data line 13, and the gate thereof is connected to a word line 16. A back-gate voltage VBB is applied to the substrate of the cell transistor 12. A differential amplifier 14 is connected to the data line 13 via an N-channel MOSFET 15, which functions as a switching element to allow a plurality of data lines 13 to share the differential amplifier 14. A selection signal BT is applied to the gate of the N-channel MOSFET 15. Hereinafter, the N-channel MOSFET 15 is referred to as a BT gate. The differential amplifier 14 performs amplification by comparing a variation in the potential of the data line 13 with the potential of the reference point.
For the sake of simplicity, let us use three power-supply voltages VCC, VSS, and VBB (VCC&gt;VSS&gt;VBB). A description will first be given, with reference to FIG. 2, of the operation of the differential amplifier 14 in which the amplifier 14 amplifies data "0" on the data line 13 and writes the data "0" to one memory cell. Before the write operation begins, the data line 13 is set to the reference potential (e.g., VCC/2). The power supply voltage VCC is applied to the gate of the BT gate 15 and the gate of the cell transistor 12 to be selected. This power supply voltage VCC may be either an external power-supply voltage or an internal power-supply voltage generated inside the semiconductor memory device. The differential amplifier 14 raises the potential of the data line 13 to the power supply voltage VCC and lowers the potential at the reference point to the power supply voltage VSS. Thus, the data "0" is written to the memory cell at full level. The potential of the word line 16 is decreased to the power supply voltage VSS and the selection signal BT is decreased to the power supply voltage VSS.
In the above manner, the back-gate voltage VBB which is a negative voltage lower than the power supply voltage VSS is needed to apply a reverse voltage to the memory cell in which the data "0" has been stored. As will be described later, the semiconductor memory device has an internal power supply which generates the negative voltage VBB.
FIG. 4 shows the operation of the differential amplifier 14 in which it amplifies data "1" on the data line 13 and writes the data "1" to the selected memory cell. The power supply voltage VCC is applied to the gate of the BT gate 15 and the gate of the cell transistor 12 to be selected. In this case, the data "1" cannot be written to the memory cell at full level, and the potential of the memory cell depends on the absolute value of either the threshold voltage of the BT gate 15 or the threshold voltage of the cell transistor 12. When the absolute value of the threshold voltage of the BT gate 15 is greater than that of the threshold value of the cell transistor 12, the potential of the memory cell depends on the absolute value of the threshold voltage of the BT gate 15. When the absolute value of the threshold voltage of the cell transistor 12 is greater than that of the threshold voltage of the BT gate 15, the potential of the memory cell depends on the absolute value of the threshold voltage of the cell transistor 12. Provided that the BT gate 15 and the cell transistor 12 have the same threshold voltage Vth, the potential in the memory cell rises only to VCC-Vth, as shown in FIG. 3. Thus, the difference in voltage between data "0" and "1" is VCC-Vth-VSS, i.e., VCC-Vth.
In the operation described above, the word line 16 is continuously set to the power supply voltage VSS at unselected memory cells. Therefore, the cell transistors are in the off state irrespective of whether the data in the memory cells is VSS or VCC-Vth, and are not affected at all even if the potential on the data line 13 fluctuates between VSS and VCC-Vth.
FIG. 3 is a block diagram of a conventional DRAM device having the circuit shown in FIG. 1. In FIG. 4, the DRAM device comprises an address buffer/pre-decoder 21, a row decoder 22, a column decoder 23, a sense amplifier and I/O gate 24, a memory cell array 25, a write clock generator 26, a data input buffer 27, and a data output buffer 28. Further, the DRAM device shown in FIG. 4 has clock generators 29 (No. 1) and 30 (No. 2). Furthermore, the DRAM device has an internal VCC generator 31, a VBB generator 32, a VPP generator 33, and a VPC/VPR voltage generator 34.
The address buffer/pre-decoder 21, in accordance with a timing signal (responding to a column address strobe signal/CAS, which denotes the inverted version of signal CAS) generated by the clock generator 30, latches an external address signal and outputs a pre-decoded address signal. The row decoder 22, in accordance with a timing signal (responding to a row address strobe signal /RAS generated by the clock generator 29), receives a pre-decoded row address and selectively drives the word lines connected to the memory cell array 25. The column decoder 23, in accordance with a timing signal from the clock generator 30, receives a pre-decoded column address and selectively drives data lines connected to the memory cell array 25.
The write clock generator 26, based on a timing signal from the clock generator 30 and a write enable signal /WE, activates the data input buffer 27. Input (write) data Din from outside of the DRAM device is written into a designated memory cell via the data input buffer 27 and the sense amplifier and I/O gate 24. The data output buffer 28 is activated by a timing signal from the clock generator 30 and a timing signal from the write clock generator 26 and outputs, as Dout, data read from the memory cell array 25 to outside.
The internal VCC generator 31 outputs an internal power supply voltage (e.g., 3.3 V) from an external power supply voltage (e.g., 5 V). It should be noted that this internal power supply voltage is sometimes referred to in the specification simply as power supply voltage VCC. The internal power supply voltage VCC is distributed to various parts in the routes shown in the figure. The VBB generator 32 generates the aforementioned negative back-gate voltage VBB and outputs it to the memory cell 25. The VPC/VPR generator 34 generates voltages VPC and VPR, both of which voltages are, for example, half the internal power supply voltage VCC (VCC/2), and outputs them as pre-charge voltages to the sense amplifier and I/O gate 24 and the memory cell array 25.
The VPP generator 33 generates a voltage VPP higher than the internal power supply voltage VCC and outputs it to the row decoder 22. As shown in FIG. 2, the potential of the memory cell is VCC-Vth when data "1" is written therein. In practical terms, the larger the difference in potential between data "0" and "1", the better. Generally, the above potential difference is set equal to VCC. The voltage VPP is used to set the word line 16 and the gate of the BT gate 15 to potentials greater than VCC and turn hard on the cell transistor 12 and the BT gate 15 and to thereby set the potential of the memory cell to VCC. The voltage VPP may be, for example, VCC +Vth, in which Vth represents the threshold voltages of the cell transistor 12 and BT gate 15.
The prior-art semiconductor memory device has the following disadvantage. As shown in FIG. 3, the conventional semiconductor memory device has many internal power supplies (31-34 in FIG. 3). These internal power supplies consume large amounts of current in the standby state, and prevent reduction in power wastage and reduction in the device size.